1. Field of the Invention
This invention relates to a column electrode driving circuit for a display apparatus, and more particularly it relates to a column electrode driving circuit for a matrix type display apparatus such as a liquid crystal display (LCD) apparatus.
2. Description of the Prior Art
An LCD apparatus is shown in FIG. 11 as a typical example of a matrix type display apparatus.
The LCD apparatus of FIG. 11 comprises a liquid crystal panel 110 in which pixel electrodes 113 are arranged in a matrix, a row electrode driving circuit 115, a column electrode driving circuit 116, and a control column 117. The liquid crystal panel 110 comprises two opposing substrates, one of which has a plurality of row electrodes 111 and a plurality of column electrodes 112 intersecting the row electrodes 111. At each of the intersections of the row electrodes 111 and column electrodes 112, a transistor 114 is provided for applying a video signal to one of the pixel electrodes 113 through the corresponding column electrode 112. Namely, a plurality of the pixel electrodes 113 constituting one column are connected to one column electrode 112.
The row electrode driving circuit 115 sequentially supplies scanning pulses to the row electrodes 111, and the column electrode diving circuit 116 supplies a video signal which is a voltage signal to be applied to the pixel electrodes 113, to the column videos 112. When the row video driving circuit 115 supplies a scanning pulse to a certain row electrode 111, the transistors 114 the gate of which is connected to that row electrode 111 are turned ON, and video signals on the column electrodes 112 are transmitted to the pixel electrodes 113 connected to the transistors 114 in ON state. The operation of the row electrode driving circuit 115 and column electrode driving circuit 116 is controlled by the control circuit 117.
A matrix type LCD apparatus such as that shown in FIG. 11 in which very pixel is provided with a transistor 114 is capable of displaying images in high contrast by means of the switching function of the transistors 114 even in cases in which multiplex drive of a plurality of row electrodes 111 is performed, and therefore it is widely used as a display unit in a portable electronic apparatus and many other electronic apparatus.
FIG. 12 shows the configuration of the column electrode driving circuit 116. The column electrode driving circuit 116 simultaneously processes video signals for two rows of the pixel electrodes 113 (i.e., two rows of pixels), and comprises a shift register 121, two sample-hold circuits 122A and 122B, and two output buffer circuits 123A and 123B.
In the shift register 121, a sampling signal S input from an external unit is shifted in accordance with a clock signal .phi. so that sampling signals q.sub.1, q.sub.2, . . . , q.sub.n are sequentially output. The sample-hold circuit 122A samples and holds the voltage component of a video signal V.sub.A non the basis of the sampling signals q.sub.1 to q.sub.n, and outputs voltage signals QA.sub.1 to QA.sub.n. The other sample-hold circuit 122B samples and holds the voltage component of a video signal V.sub.B on the basis of the sampling signals q.sub.1 and q.sub.n, and outputs voltage signals QB.sub.1 to QB.sub.n. Each of the voltage signals QA.sub.1 to QA.sub.n and QB.sub.1 to QB.sub.n has a level which is substantially equal to the respective voltage level held in the circuits 122A and 122B. The output buffer circuit 123A takes in the voltage signals QA.sub.1 to QN.sub.n according to an output pulse T, and outputs them in parallel to the column electrodes 112 during the period the level of a selection signal U is positive. In contrast, the output buffer circuit 123B takes in the voltage signals QB.sub.1 to QB.sub.n according to the output pulse T, and outputs them in parallel to the column electrodes 112 during the period the level of the selection signal U is negative.
The operation of the column electrode driving circuit 116 will be described with reference to FIG. 13. The video signals V.sub.A and V.sub.B are both input serially. In the ith sampling period, at the timing the sampling signals q.sub.1, . . . , q.sub.j, . . . , q.sub.n are output from the shift register 121, the voltage components V.sub.Ai,1, . . . , V.sub.Ai,j, . . . , V.sub.Ai,n of the video signal V.sub.A are sampled and held by the sample-hold circuit 122A. In the same sampling period, the voltage components V.sub.Bi,1, . . . , V.sub.Bi,j, . . . , V.sub.Bi,n of the video signal V.sub.B are sampled and held by the sample-hold circuit 122B. The sample-hold circuit 122A outputs the voltage signals QA.sub.j (j=1 to n) based on the held voltage V.sub.Ai,j (j=1 to n), and these voltage signals are output from the output buffer circuit 123A as the voltage signal Q.sub.j during the period the selection signal U in the first half of the next (i+1)th sampling period is positive. The sample-hold circuit 122B outputs the voltage signals QB.sub.j (j=1 to n) based on the held voltage V.sub.Bi,j (j=1 to n), and these voltage signals are output from the output buffer circuit 123B as the voltage signal Q.sub.j during the period the selection signal U in the last half of the (i+1)th sampling period is negative.
In the column electrode driving circuit 116, the video signals for two rows of the pixel electrodes 113 are sampled simultaneously. Therefore, by supplying a video signal belonging to odd fields to the column electrode driving circuit 116 as the video signal V.sub.A and supplying a video signal belonging to even fields to the column electrode driving circuit 116 as the video signal V.sub.B, a display system which receives a video signal for the non-interlace scanning and uses a field memory to perform the double-speed non-interlaced display can be easily realized without increasing the frequency of the video signal.
FIG. 14 shows another LCD apparatus having a liquid crystal panel 140 in which the pixel electrodes 113 are formed into a so-called delta arrangement. More specifically, the positions of the pixel electrodes 113 in one row are shifted along the row direction by one-half pixel from those of the pixel electrodes in the adjacent rows. In displaying images based on a television signal, the LCD apparatus of FIG. 14 having pixel electrodes with a delta arrangement is superior in display quality to the LCD apparatus of FIG. 12 with a conventional arrangement of the pixel electrodes, provided that the numbers of the pixel electrodes in both the apparatus are equal to each other.
However, in the column electrode driving circuit 116 described above, the two sample-hold circuits 122A and 122B sample a video signal with the same sampling timing, and therefore a condition in which the sampling timing of a video signal does not conform with the position of the pixel electrode corresponding to the sampled video signal occurs every other row of the pixel electrodes 113. This causes the degradation of the display quality. For this reason, the column electrode driving circuit 116 is not suitable for driving a delta-arrangement display unit such as the panel 140.
A device for driving a delta-arrangement display unit and having double-speed conversion means is disclosed in the copending U.S. patent application Ser. No. 07/659,211 filed Feb. 22, 1991 which is now U.S. Pat. No. 5,922,658.